mini_disassembler_types.h 8.3 KB

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  1. // -*- Mode: C++; c-basic-offset: 2; indent-tabs-mode: nil -*-
  2. /* Copyright (c) 2007, Google Inc.
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions are
  7. * met:
  8. *
  9. * * Redistributions of source code must retain the above copyright
  10. * notice, this list of conditions and the following disclaimer.
  11. * * Redistributions in binary form must reproduce the above
  12. * copyright notice, this list of conditions and the following disclaimer
  13. * in the documentation and/or other materials provided with the
  14. * distribution.
  15. * * Neither the name of Google Inc. nor the names of its
  16. * contributors may be used to endorse or promote products derived from
  17. * this software without specific prior written permission.
  18. *
  19. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  20. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  21. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  22. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  23. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  24. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  25. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  26. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  27. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  29. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30. *
  31. * ---
  32. * Author: Joi Sigurdsson
  33. *
  34. * Several simple types used by the disassembler and some of the patching
  35. * mechanisms.
  36. */
  37. #ifndef GOOGLE_PERFTOOLS_MINI_DISASSEMBLER_TYPES_H_
  38. #define GOOGLE_PERFTOOLS_MINI_DISASSEMBLER_TYPES_H_
  39. namespace sidestep {
  40. // Categories of instructions that we care about
  41. enum InstructionType {
  42. // This opcode is not used
  43. IT_UNUSED,
  44. // This disassembler does not recognize this opcode (error)
  45. IT_UNKNOWN,
  46. // This is not an instruction but a reference to another table
  47. IT_REFERENCE,
  48. // This byte is a prefix byte that we can ignore
  49. IT_PREFIX,
  50. // This is a prefix byte that switches to the nondefault address size
  51. IT_PREFIX_ADDRESS,
  52. // This is a prefix byte that switches to the nondefault operand size
  53. IT_PREFIX_OPERAND,
  54. // A jump or call instruction
  55. IT_JUMP,
  56. // A return instruction
  57. IT_RETURN,
  58. // Any other type of instruction (in this case we don't care what it is)
  59. IT_GENERIC,
  60. };
  61. // Lists IA-32 operand sizes in multiples of 8 bits
  62. enum OperandSize {
  63. OS_ZERO = 0,
  64. OS_BYTE = 1,
  65. OS_WORD = 2,
  66. OS_DOUBLE_WORD = 4,
  67. OS_QUAD_WORD = 8,
  68. OS_DOUBLE_QUAD_WORD = 16,
  69. OS_32_BIT_POINTER = 32/8,
  70. OS_48_BIT_POINTER = 48/8,
  71. OS_SINGLE_PRECISION_FLOATING = 32/8,
  72. OS_DOUBLE_PRECISION_FLOATING = 64/8,
  73. OS_DOUBLE_EXTENDED_PRECISION_FLOATING = 80/8,
  74. OS_128_BIT_PACKED_SINGLE_PRECISION_FLOATING = 128/8,
  75. OS_PSEUDO_DESCRIPTOR = 6
  76. };
  77. // Operand addressing methods from the IA-32 manual. The enAmMask value
  78. // is a mask for the rest. The other enumeration values are named for the
  79. // names given to the addressing methods in the manual, e.g. enAm_D is for
  80. // the D addressing method.
  81. //
  82. // The reason we use a full 4 bytes and a mask, is that we need to combine
  83. // these flags with the enOperandType to store the details
  84. // on the operand in a single integer.
  85. enum AddressingMethod {
  86. AM_NOT_USED = 0, // This operand is not used for this instruction
  87. AM_MASK = 0x00FF0000, // Mask for the rest of the values in this enumeration
  88. AM_A = 0x00010000, // A addressing type
  89. AM_C = 0x00020000, // C addressing type
  90. AM_D = 0x00030000, // D addressing type
  91. AM_E = 0x00040000, // E addressing type
  92. AM_F = 0x00050000, // F addressing type
  93. AM_G = 0x00060000, // G addressing type
  94. AM_I = 0x00070000, // I addressing type
  95. AM_J = 0x00080000, // J addressing type
  96. AM_M = 0x00090000, // M addressing type
  97. AM_O = 0x000A0000, // O addressing type
  98. AM_P = 0x000B0000, // P addressing type
  99. AM_Q = 0x000C0000, // Q addressing type
  100. AM_R = 0x000D0000, // R addressing type
  101. AM_S = 0x000E0000, // S addressing type
  102. AM_T = 0x000F0000, // T addressing type
  103. AM_V = 0x00100000, // V addressing type
  104. AM_W = 0x00110000, // W addressing type
  105. AM_X = 0x00120000, // X addressing type
  106. AM_Y = 0x00130000, // Y addressing type
  107. AM_REGISTER = 0x00140000, // Specific register is always used as this op
  108. AM_IMPLICIT = 0x00150000, // An implicit, fixed value is used
  109. };
  110. // Operand types from the IA-32 manual. The enOtMask value is
  111. // a mask for the rest. The rest of the values are named for the
  112. // names given to these operand types in the manual, e.g. enOt_ps
  113. // is for the ps operand type in the manual.
  114. //
  115. // The reason we use a full 4 bytes and a mask, is that we need
  116. // to combine these flags with the enAddressingMethod to store the details
  117. // on the operand in a single integer.
  118. enum OperandType {
  119. OT_MASK = 0xFF000000,
  120. OT_A = 0x01000000,
  121. OT_B = 0x02000000,
  122. OT_C = 0x03000000,
  123. OT_D = 0x04000000,
  124. OT_DQ = 0x05000000,
  125. OT_P = 0x06000000,
  126. OT_PI = 0x07000000,
  127. OT_PS = 0x08000000, // actually unsupported for (we don't know its size)
  128. OT_Q = 0x09000000,
  129. OT_S = 0x0A000000,
  130. OT_SS = 0x0B000000,
  131. OT_SI = 0x0C000000,
  132. OT_V = 0x0D000000,
  133. OT_W = 0x0E000000,
  134. OT_SD = 0x0F000000, // scalar double-precision floating-point value
  135. OT_PD = 0x10000000, // double-precision floating point
  136. // dummy "operand type" for address mode M - which doesn't specify
  137. // operand type
  138. OT_ADDRESS_MODE_M = 0x80000000
  139. };
  140. // Flag that indicates if an immediate operand is 64-bits.
  141. //
  142. // The Intel 64 and IA-32 Architecture Software Developer's Manual currently
  143. // defines MOV as the only instruction supporting a 64-bit immediate operand.
  144. enum ImmediateOperandSize {
  145. IOS_MASK = 0x0000F000,
  146. IOS_DEFAULT = 0x0,
  147. IOS_64 = 0x00001000
  148. };
  149. // Everything that's in an Opcode (see below) except the three
  150. // alternative opcode structs for different prefixes.
  151. struct SpecificOpcode {
  152. // Index to continuation table, or 0 if this is the last
  153. // byte in the opcode.
  154. int table_index_;
  155. // The opcode type
  156. InstructionType type_;
  157. // Description of the type of the dest, src and aux operands,
  158. // put together from enOperandType, enAddressingMethod and
  159. // enImmediateOperandSize flags.
  160. int flag_dest_;
  161. int flag_source_;
  162. int flag_aux_;
  163. // We indicate the mnemonic for debugging purposes
  164. const char* mnemonic_;
  165. };
  166. // The information we keep in our tables about each of the different
  167. // valid instructions recognized by the IA-32 architecture.
  168. struct Opcode {
  169. // Index to continuation table, or 0 if this is the last
  170. // byte in the opcode.
  171. int table_index_;
  172. // The opcode type
  173. InstructionType type_;
  174. // Description of the type of the dest, src and aux operands,
  175. // put together from an enOperandType flag and an enAddressingMethod
  176. // flag.
  177. int flag_dest_;
  178. int flag_source_;
  179. int flag_aux_;
  180. // We indicate the mnemonic for debugging purposes
  181. const char* mnemonic_;
  182. // Alternative opcode info if certain prefixes are specified.
  183. // In most cases, all of these are zeroed-out. Only used if
  184. // bPrefixDependent is true.
  185. bool is_prefix_dependent_;
  186. SpecificOpcode opcode_if_f2_prefix_;
  187. SpecificOpcode opcode_if_f3_prefix_;
  188. SpecificOpcode opcode_if_66_prefix_;
  189. };
  190. // Information about each table entry.
  191. struct OpcodeTable {
  192. // Table of instruction entries
  193. const Opcode* table_;
  194. // How many bytes left to shift ModR/M byte <b>before</b> applying mask
  195. unsigned char shift_;
  196. // Mask to apply to byte being looked at before comparing to table
  197. unsigned char mask_;
  198. // Minimum/maximum indexes in table.
  199. unsigned char min_lim_;
  200. unsigned char max_lim_;
  201. };
  202. // Information about each entry in table used to decode ModR/M byte.
  203. struct ModrmEntry {
  204. // Is the operand encoded as bytes in the instruction (rather than
  205. // if it's e.g. a register in which case it's just encoded in the
  206. // ModR/M byte)
  207. bool is_encoded_in_instruction_;
  208. // Is there a SIB byte? In this case we always need to decode it.
  209. bool use_sib_byte_;
  210. // What is the size of the operand (only important if it's encoded
  211. // in the instruction)?
  212. OperandSize operand_size_;
  213. };
  214. }; // namespace sidestep
  215. #endif // GOOGLE_PERFTOOLS_MINI_DISASSEMBLER_TYPES_H_