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-/* Copyright (C) 2014 OSCAR lab, Stony Brook University
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- This file is part of Graphene Library OS.
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-
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- Graphene Library OS is free software: you can redistribute it and/or
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- modify it under the terms of the GNU General Public License
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- as published by the Free Software Foundation, either version 3 of the
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- License, or (at your option) any later version.
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-
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- Graphene Library OS is distributed in the hope that it will be useful,
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- but WITHOUT ANY WARRANTY; without even the implied warranty of
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- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- GNU General Public License for more details.
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-
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- You should have received a copy of the GNU General Public License
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- along with this program. If not, see <http://www.gnu.org/licenses/>. */
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-
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-/*
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- * cmpxchg_32.h
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- */
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-
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-#ifndef _ASM_X86_CMPXCHG_32_H
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-#define _ASM_X86_CMPXCHG_32_H
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-
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-#define LOCK_PREFIX "\n\tlock; "
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-/*
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- * Note: if you use set64_bit(), __cmpxchg64(), or their variants, you
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- * you need to test for the feature in boot_cpu_data.
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- */
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-
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-extern void __xchg_wrong_size(void);
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-
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-/*
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- * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
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- * Note 2: xchg has side effect, so that attribute volatile is necessary,
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- * but generally the primitive is invalid, *ptr is output argument. --ANK
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- */
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-
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-struct __xchg_dummy {
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- unsigned long a[100];
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-};
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-#define __xg(x) ((struct __xchg_dummy *)(x))
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-
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-#define __xchg(x, ptr, size) \
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-({ \
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- __typeof(*(ptr)) __x = (x); \
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- switch (size) { \
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- case 1: \
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- asm volatile("lock; xchgb %b0,%1" \
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- : "=q" (__x), "+m" (*__xg(ptr)) \
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- : "0" (__x) \
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- : "memory"); \
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- break; \
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- case 2: \
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- asm volatile("lock; xchgw %w0,%1" \
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- : "=r" (__x), "+m" (*__xg(ptr)) \
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- : "0" (__x) \
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- : "memory"); \
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- break; \
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- case 4: \
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- asm volatile("lock; xchgl %0,%1" \
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- : "=r" (__x), "+m" (*__xg(ptr)) \
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- : "0" (__x) \
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- : "memory"); \
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- break; \
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- default: \
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- __xchg_wrong_size(); \
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- } \
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- __x; \
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-})
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-
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-#define xchg(ptr, v) \
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- __xchg((v), (ptr), sizeof(*ptr))
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-
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-/*
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- * CMPXCHG8B only writes to the target if we had the previous
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- * value in registers, otherwise it acts as a read and gives us the
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- * "new previous" value. That is why there is a loop. Preloading
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- * EDX:EAX is a performance optimization: in the common case it means
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- * we need only one locked operation.
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- *
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- * A SIMD/3DNOW!/MMX/FPU 64-bit store here would require at the very
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- * least an FPU save and/or %cr0.ts manipulation.
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- *
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- * cmpxchg8b must be used with the lock prefix here to allow the
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- * instruction to be executed atomically. We need to have the reader
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- * side to see the coherent 64bit value.
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- */
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-static inline void set_64bit(volatile u64 *ptr, u64 value)
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-{
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- u32 low = value;
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- u32 high = value >> 32;
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- u64 prev = *ptr;
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-
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- asm volatile("\n1:\t"
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- LOCK_PREFIX "cmpxchg8b %0\n\t"
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- "jnz 1b"
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- : "=m" (*ptr), "+A" (prev)
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- : "b" (low), "c" (high)
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- : "memory");
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-}
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-
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-extern void __cmpxchg_wrong_size(void);
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-
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-/*
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- * Atomic compare and exchange. Compare OLD with MEM, if identical,
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- * store NEW in MEM. Return the initial value in MEM. Success is
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- * indicated by comparing RETURN with OLD.
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- */
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-#define __raw_cmpxchg(ptr, old, new, size, lock) \
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-({ \
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- __typeof__(*(ptr)) __ret; \
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- __typeof__(*(ptr)) __old = (old); \
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- __typeof__(*(ptr)) __new = (new); \
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- switch (size) { \
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- case 1: \
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- asm volatile(lock "cmpxchgb %b2,%1" \
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- : "=a" (__ret), "+m" (*__xg(ptr)) \
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- : "q" (__new), "0" (__old) \
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- : "memory"); \
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- break; \
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- case 2: \
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- asm volatile(lock "cmpxchgw %w2,%1" \
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- : "=a" (__ret), "+m" (*__xg(ptr)) \
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- : "r" (__new), "0" (__old) \
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- : "memory"); \
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- break; \
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- case 4: \
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- asm volatile(lock "cmpxchgl %2,%1" \
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- : "=a" (__ret), "+m" (*__xg(ptr)) \
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- : "r" (__new), "0" (__old) \
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- : "memory"); \
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- break; \
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- default: \
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- __cmpxchg_wrong_size(); \
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- } \
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- __ret; \
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-})
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-
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-#define __cmpxchg(ptr, old, new, size) \
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- __raw_cmpxchg((ptr), (old), (new), (size), LOCK_PREFIX)
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-
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-#define __sync_cmpxchg(ptr, old, new, size) \
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- __raw_cmpxchg((ptr), (old), (new), (size), "lock; ")
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-
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-#define __cmpxchg_local(ptr, old, new, size) \
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- __raw_cmpxchg((ptr), (old), (new), (size), "")
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-
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-#ifdef CONFIG_X86_CMPXCHG
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-#define __HAVE_ARCH_CMPXCHG 1
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-
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-#define cmpxchg(ptr, old, new) \
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- __cmpxchg((ptr), (old), (new), sizeof(*ptr))
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-
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-#define sync_cmpxchg(ptr, old, new) \
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- __sync_cmpxchg((ptr), (old), (new), sizeof(*ptr))
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-
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-#define cmpxchg_local(ptr, old, new) \
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- __cmpxchg_local((ptr), (old), (new), sizeof(*ptr))
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-#endif
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-
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-#ifdef CONFIG_X86_CMPXCHG64
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-#define cmpxchg64(ptr, o, n) \
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- ((__typeof__(*(ptr)))__cmpxchg64((ptr), (unsigned long long)(o), \
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- (unsigned long long)(n)))
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-#define cmpxchg64_local(ptr, o, n) \
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- ((__typeof__(*(ptr)))__cmpxchg64_local((ptr), (unsigned long long)(o), \
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- (unsigned long long)(n)))
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-#endif
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-
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-static inline unsigned long long __cmpxchg64(volatile void *ptr,
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- unsigned long long old,
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- unsigned long long new)
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-{
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- unsigned long long prev;
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- asm volatile(LOCK_PREFIX "cmpxchg8b %1"
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- : "=A" (prev),
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- "+m" (*__xg(ptr))
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- : "b" ((unsigned long)new),
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- "c" ((unsigned long)(new >> 32)),
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- "0" (old)
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- : "memory");
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- return prev;
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-}
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-
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-static inline unsigned long long __cmpxchg64_local(volatile void *ptr,
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- unsigned long long old,
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- unsigned long long new)
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-{
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- unsigned long long prev;
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- asm volatile("cmpxchg8b %1"
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- : "=A" (prev),
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- "+m" (*__xg(ptr))
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- : "b" ((unsigned long)new),
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- "c" ((unsigned long)(new >> 32)),
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- "0" (old)
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- : "memory");
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- return prev;
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-}
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-
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-#ifndef CONFIG_X86_CMPXCHG
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-/*
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- * Building a kernel capable running on 80386. It may be necessary to
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- * simulate the cmpxchg on the 80386 CPU. For that purpose we define
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- * a function for each of the sizes we support.
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- */
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-
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-extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
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-extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
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-extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
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-
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-static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
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- unsigned long new, int size)
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-{
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- switch (size) {
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- case 1:
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- return cmpxchg_386_u8(ptr, old, new);
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- case 2:
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- return cmpxchg_386_u16(ptr, old, new);
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- case 4:
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- return cmpxchg_386_u32(ptr, old, new);
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- }
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- return old;
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-}
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-
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-#define cmpxchg(ptr, o, n) \
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-({ \
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- __typeof__(*(ptr)) __ret; \
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- if (likely(boot_cpu_data.x86 > 3)) \
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- __ret = (__typeof__(*(ptr)))__cmpxchg((ptr), \
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- (unsigned long)(o), (unsigned long)(n), \
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- sizeof(*(ptr))); \
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- else \
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- __ret = (__typeof__(*(ptr)))cmpxchg_386((ptr), \
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- (unsigned long)(o), (unsigned long)(n), \
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- sizeof(*(ptr))); \
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- __ret; \
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-})
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-#define cmpxchg_local(ptr, o, n) \
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-({ \
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- __typeof__(*(ptr)) __ret; \
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- if (likely(boot_cpu_data.x86 > 3)) \
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- __ret = (__typeof__(*(ptr)))__cmpxchg_local((ptr), \
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- (unsigned long)(o), (unsigned long)(n), \
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- sizeof(*(ptr))); \
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- else \
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- __ret = (__typeof__(*(ptr)))cmpxchg_386((ptr), \
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- (unsigned long)(o), (unsigned long)(n), \
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- sizeof(*(ptr))); \
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- __ret; \
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-})
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-#endif
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-
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-#ifndef CONFIG_X86_CMPXCHG64
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-/*
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- * Building a kernel capable running on 80386 and 80486. It may be necessary
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- * to simulate the cmpxchg8b on the 80386 and 80486 CPU.
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- */
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-
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-extern unsigned long long cmpxchg_486_u64(volatile void *, u64, u64);
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-
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-#define cmpxchg64(ptr, o, n) \
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-({ \
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- __typeof__(*(ptr)) __ret; \
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- __typeof__(*(ptr)) __old = (o); \
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- __typeof__(*(ptr)) __new = (n); \
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- alternative_io(LOCK_PREFIX_HERE \
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- "call cmpxchg8b_emu", \
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- "lock; cmpxchg8b (%%esi)" , \
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- X86_FEATURE_CX8, \
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- "=A" (__ret), \
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- "S" ((ptr)), "0" (__old), \
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- "b" ((unsigned int)__new), \
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- "c" ((unsigned int)(__new>>32)) \
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- : "memory"); \
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- __ret; })
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-
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-
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-
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-#define cmpxchg64_local(ptr, o, n) \
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-({ \
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- __typeof__(*(ptr)) __ret; \
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- if (likely(boot_cpu_data.x86 > 4)) \
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- __ret = (__typeof__(*(ptr)))__cmpxchg64_local((ptr), \
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- (unsigned long long)(o), \
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- (unsigned long long)(n)); \
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- else \
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- __ret = (__typeof__(*(ptr)))cmpxchg_486_u64((ptr), \
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- (unsigned long long)(o), \
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- (unsigned long long)(n)); \
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- __ret; \
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-})
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-
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-#endif
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-
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-#endif /* _ASM_X86_CMPXCHG_32_H */
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Don Porter