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+/*
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+* Copyright 2011-2017 Intel Corporation
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+*
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+* Redistribution and use in source and binary forms, with or without
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+* modification, are permitted provided that the following conditions
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+* are met:
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+*
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+* 1. Redistributions of source code must retain the above copyright notice,
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+* this list of conditions and the following disclaimer.
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+*
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+* 2. Redistributions in binary form must reproduce the above copyright
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+* notice, this list of conditions and the following disclaimer in the
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+* documentation and/or other materials provided with the distribution.
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+*
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+* 3. Neither the name of the copyright holder nor the names of its
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+* contributors may be used to endorse or promote products derived from
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+* this software without specific prior written permission.
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+*
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+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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+* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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+* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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+* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+*/
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+
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+#include <sys/stat.h>
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+#include <sys/types.h>
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+#include <stdio.h>
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+#include <unistd.h>
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+#include <errno.h>
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+#include <sgx_uae_service.h>
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+#include <sgx_capable.h>
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+
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+/* __cpuid(unsinged int info[4], unsigned int leaf, unsigned int subleaf); */
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+/* Because gcc's __get_cpuid() intrinsic is difficult to work with */
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+#define __cpuid(x,y,z) asm volatile("cpuid":"=a"(x[0]),"=b"(x[1]),"=c"(x[2]),"=d"(x[3]):"a"(y),"c"(z))
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+
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+#define EFIFS_PATH "/sys/firmware/efi/"
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+#define EFIVARS_PATH EFIFS_PATH"efivars/"
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+#define EFIVAR_EPCBIOS EFIVARS_PATH"EPCBIOS-c60aa7f6-e8d6-4956-8ba1-fe26298f5e87"
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+#define EFIVAR_EPCSW EFIVARS_PATH"EPCSW-d69a279b-58eb-45d1-a148-771bb9eb5251"
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+
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+static int _is_sgx_available();
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+static int _is_cpu_supported();
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+
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+sgx_status_t sgx_is_capable (int *sgx_capable)
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+{
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+ struct stat sb;
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+
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+ if ( sgx_capable == NULL ) return SGX_ERROR_INVALID_PARAMETER;
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+
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+ if ( ! _is_cpu_supported() ) {
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+ *sgx_capable= 0;
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+ return SGX_SUCCESS;
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+ }
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+
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+ if ( _is_sgx_available() ) {
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+ *sgx_capable= 1;
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+ return SGX_SUCCESS;
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+ }
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+
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+ /* Check to see if the Software Control Interface is available */
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+
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+ if ( stat(EFIVAR_EPCBIOS, &sb) == -1 ) {
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+ if ( errno == EACCES ) return SGX_ERROR_NO_PRIVILEGE;
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+ *sgx_capable = 0;
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+ return SGX_SUCCESS;
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+ }
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+
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+ *sgx_capable= 1;
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+ return SGX_SUCCESS;
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+}
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+
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+sgx_status_t sgx_cap_get_status (sgx_device_status_t *sgx_device_status)
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+{
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+ struct stat sb;
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+ int has_efifs= 0;
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+
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+ if ( sgx_device_status == NULL ) return SGX_ERROR_INVALID_PARAMETER;
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+
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+ if ( ! _is_cpu_supported() ) {
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+ *sgx_device_status= SGX_DISABLED_UNSUPPORTED_CPU;
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+ return SGX_SUCCESS;
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+ }
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+
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+ if ( _is_sgx_available() ) {
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+ *sgx_device_status= SGX_ENABLED;
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+ return SGX_SUCCESS;
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+ }
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+
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+ /*
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+ * Intel SGX is supported, but not enabled. Figure out what
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+ * it will take to enable it.
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+ */
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+
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+ /* Were we booted in UEFI mode? */
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+
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+ if ( stat(EFIFS_PATH, &sb) == 0 ) {
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+ has_efifs= 1;
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+
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+ if ( stat(EFIVARS_PATH, &sb) == -1 )
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+ {
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+ /* We have /sys/firmware/efi but not efivars */
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+
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+ switch (errno) {
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+ case EACCES:
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+ return SGX_ERROR_NO_PRIVILEGE;
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+ case ENOENT:
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+ case ENOTDIR:
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+ break;
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+ default:
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+ return SGX_ERROR_UNEXPECTED;
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+ }
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+ }
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+ } else {
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+ switch (errno) {
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+ case EACCES:
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+ return SGX_ERROR_NO_PRIVILEGE;
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+ case ENOENT:
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+ case ENOTDIR:
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+ break;
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+ default:
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+ return SGX_ERROR_UNEXPECTED;
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+ }
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+ }
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+
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+ if ( ! has_efifs ) {
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+ /*
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+ * We don't have /sys/firmware/efi mounted. It could have been
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+ * unmounted by the user, or we might not have UEFI support in
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+ * the OS. If /boot/efi exists, then we are probably capable of
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+ * UEFI and should report SGX_DISABLED. Otherwise report
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+ * SGX_DISABLED_LEGACY_OS.
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+ */
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+
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+ if ( stat("/boot/efi", &sb) == 0 ) *sgx_device_status= SGX_DISABLED;
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+ else {
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+ switch(errno) {
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+ case ENOENT:
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+ case ENOTDIR:
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+ *sgx_device_status= SGX_DISABLED_LEGACY_OS;
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+ break;
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+ default:
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+ /*
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+ * We don't have enough information to figure this out
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+ * so report SGX_DISABLED.
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+ */
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+ *sgx_device_status= SGX_DISABLED;
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+ }
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+
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+ }
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+
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+ return SGX_SUCCESS;
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+ }
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+
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+ /*
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+ * We have access to efivars. Now examine the EFI variable for the
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+ * Software Control Interface.
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+ */
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+
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+ if ( stat(EFIVAR_EPCBIOS, &sb) == -1 ) {
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+ if ( errno == EACCES ) return SGX_ERROR_NO_PRIVILEGE;
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+
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+ /* No SCI is present so we can't do a s/w enabled */
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+
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+ *sgx_device_status= SGX_DISABLED_MANUAL_ENABLE;
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+ return SGX_SUCCESS;
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+ }
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+
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+ /*
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+ * Check to see if the software enable has already been
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+ * performed. If so, then we will be enabled on the next
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+ * reboot.
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+ */
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+
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+ if ( stat(EFIVAR_EPCSW, &sb) == -1 ) {
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+ if ( errno == EACCES ) return SGX_ERROR_NO_PRIVILEGE;
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+
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+ /* The software enable hasn't been attempted yet. */
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+
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+ *sgx_device_status= SGX_DISABLED_SCI_AVAILABLE;
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+ return SGX_SUCCESS;
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+ }
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+
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+ /* Software enable has occurred. Need a reboot. */
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+
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+ *sgx_device_status= SGX_DISABLED_REBOOT_REQUIRED;
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+
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+ return SGX_SUCCESS;
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+}
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+
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+/* Determine if the CPU supports Intel SGX */
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+
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+static int _is_cpu_supported()
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+{
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+ unsigned int info[4];
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+ unsigned int *ebx, *ecx, *edx;
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+
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+ ebx= &info[1];
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+ ecx= &info[2];
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+ edx= &info[3];
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+
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+ /* Is this an Intel CPU? */
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+
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+ __cpuid (info, 0x00, 0);
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+ if ( *ebx != 0x756e6547 || *ecx != 0x6c65746e || *edx != 0x49656e69 )
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+ return 0;
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+
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+ /* Does the CPU support Intel SGX? */
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+
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+ __cpuid (info, 0x07, 0);
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+
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+ return ( *ebx & (0x1<<2) );
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+}
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+
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+/* Are SGX instructions available for use? */
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+
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+static int _is_sgx_available ()
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+{
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+ unsigned int info[4];
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+ unsigned int *eax, *ebx, *ecx, *edx;
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+ unsigned int subleaf= 2;
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+ unsigned int flag;
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+
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+ eax= &info[0];
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+ ebx= &info[1];
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+ ecx= &info[2];
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+ edx= &info[3];
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+
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+ /* Are Intel SGX instructions available for use? */
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+
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+ __cpuid(info, 0x12, 0);
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+
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+ flag= *eax&0x3;
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+ if ( flag == 0 ) return 0;
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+
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+ /* Do we have non-zero, max enclave sizes? */
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+
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+ if ( (*edx & 0xFFFF) == 0 ) return 0;
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+
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+ /*
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+ * Enumerate the subleafs for the EPC. At least one must be a valid
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+ * subleaf that describes a page.
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+ */
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+
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+ while (1) {
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+ __cpuid(info, 0x12, subleaf);
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+
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+ /*
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+ * Is this an invalid subleaf? If we've hit an invalid subleaf
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+ * before finding a valid subleaf with a non-zero page size,
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+ * then we have no EPC memory allocated, and thus no Intel SGX
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+ * capability.
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+ */
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+
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+ if ( ! (*eax & 0x1) ) return 0;
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+
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+ /*
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+ * Is there a non-zero size for this EPC subleaf? If so, we
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+ * have memory allocated to the EPC for Intel SGX, and are
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+ * enabled.
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+ */
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+
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+ if (
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+ (*eax&0xFFFFF000 || *ebx&0xFFFFF) &&
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+ (*ecx&0xFFFFF000 || *edx&0xFFFFF)
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+ ) return 1;
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+
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+ ++subleaf;
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+ }
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+
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+ /* We'll never get here, but we need to keep the compiler happy */
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+
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+ return 0;
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+}
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+
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+sgx_status_t sgx_cap_enable_device (sgx_device_status_t *sgx_device_status)
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+{
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+ sgx_status_t status;
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+ struct epcbios_stuct {
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+ uint32_t attrs;
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+ uint32_t sprmbins;
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+ uint32_t maxepcsz;
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+ /* There's more, but this is all we need */
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+ } epcbios;
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+ struct epcsw_struct {
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+ uint32_t attrs;
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+ uint32_t maxepcsz;
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+ } epcsw;
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+ FILE *fefivar;
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+
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+ if ( sgx_device_status == NULL ) return SGX_ERROR_INVALID_PARAMETER;
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+
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+ status= sgx_cap_get_status(sgx_device_status);
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+ if ( status != SGX_SUCCESS ) return status;
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+
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+ /*
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+ * If we get back anything other than SGX_DISABLED_SCI_AVAILABLE
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+ * then return, because there is nothing to do.
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+ */
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+
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+ if ( *sgx_device_status != SGX_DISABLED_SCI_AVAILABLE )
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+ return SGX_SUCCESS;
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+
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+ /* Attempt the software enable */
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+
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+ /* First, read the EPCBIOS EFI variable to get the max EPC size */
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+
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+ fefivar= fopen(EFIVAR_EPCBIOS, "r");
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+ if ( fefivar == NULL ) {
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+ if ( errno == EACCES ) return SGX_ERROR_NO_PRIVILEGE;
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+
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+ return SGX_ERROR_UNEXPECTED;
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+ }
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+
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+ /*
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+ * The first 4 bytes are the EFI variable attributes. Data starts
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+ * at offset 0x4, and the value we want is a UINT32 at offset 0x8.
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+ */
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+
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+ if ( fread(&epcbios, sizeof(epcbios), 1, fefivar) != 1 ) {
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+ fclose(fefivar);
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+ return SGX_ERROR_UNEXPECTED;
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+ }
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+
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+ fclose(fefivar);
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+
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+ /*
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+ * Now create the EPCSW EFI variable. The variable data is a
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+ * single UINT32 specifying the requested EPC size.
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+ */
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+
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+ epcsw.attrs= epcbios.attrs;
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+ epcsw.maxepcsz= epcbios.maxepcsz;
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+
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+ fefivar= fopen(EFIVAR_EPCSW, "w");
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+ if ( fefivar == NULL ) {
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+ if ( errno == EACCES ) return SGX_ERROR_NO_PRIVILEGE;
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+
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+ return SGX_ERROR_UNEXPECTED;
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+ }
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+
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+ /* Write out the EPCSW structure */
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+
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+ if ( fwrite(&epcsw, sizeof(epcsw), 1, fefivar) != 1 ) {
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+ unlink(EFIVAR_EPCSW);
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+ fclose(fefivar);
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+ return SGX_ERROR_UNEXPECTED;
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+ }
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+
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+ fclose(fefivar);
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+
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+ *sgx_device_status= SGX_DISABLED_REBOOT_REQUIRED;
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+
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+ return SGX_SUCCESS;
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+}
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John Mechalas