cpudef.h 10 KB

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  1. /*
  2. * Copyright (C) 2016 Intel Corporation. All rights reserved.
  3. *
  4. * Redistribution and use in source and binary forms, with or without
  5. * modification, are permitted provided that the following conditions
  6. * are met:
  7. *
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in
  12. * the documentation and/or other materials provided with the
  13. * distribution.
  14. * * Neither the name of Intel Corporation nor the names of its
  15. * contributors may be used to endorse or promote products derived
  16. * from this software without specific prior written permission.
  17. *
  18. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  28. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29. *
  30. */
  31. #ifndef __CPUDEF_H__
  32. #define __CPUDEF_H__
  33. #include "ippcore.h"
  34. #if defined( __cplusplus )
  35. extern "C" {
  36. #endif
  37. #undef __CDECL
  38. #if defined( _WIN32 ) || defined ( _WIN64 )
  39. #define __CDECL __cdecl
  40. #else
  41. #define __CDECL
  42. #endif
  43. /* Intel CPU informator */
  44. typedef struct {
  45. int family;
  46. int stepping;
  47. int model;
  48. int type;
  49. int feature;
  50. int tlb;
  51. int cache;
  52. int mmx;
  53. int freq;
  54. int ssx;
  55. int wni;
  56. int htt;
  57. int pni;
  58. int em64t;
  59. int mni;
  60. int phcores;
  61. int sse41;
  62. int sse42;
  63. int ext_family;
  64. int ext_model;
  65. int movbe_instr;
  66. int avx;
  67. int xsavexgetbv;
  68. } ippIntelCpuId;
  69. int __CDECL ownGetMaskFeatures( Ipp64u* pFeaturesMask );
  70. int __CDECL ownGetFeature( Ipp64u MaskOfFeature );
  71. int __CDECL ipp_is_avx_extension( void );
  72. __INT64 __CDECL ipp_get_pentium_counter (void);
  73. int __CDECL ipp_is_mmx_extension (void);
  74. int __CDECL ipp_is_ssx_extension (void);
  75. int __CDECL ipp_is_wni_extension (void);
  76. int __CDECL ipp_is_htt_extension( void );
  77. int __CDECL ipp_is_pni_extension( void );
  78. int __CDECL ipp_is_mni_extension( void );
  79. int __CDECL ipp_is_sse41_extension( void );
  80. int __CDECL ipp_is_sse42_extension( void );
  81. int __CDECL ipp_is_movbe( void );
  82. int __CDECL ipp_get_cores_on_die( void );
  83. int __CDECL ipp_is_em64t_extension( void );
  84. int __CDECL ipp_has_cpuid ( void );
  85. int __CDECL ipp_has_rdtsc( void );
  86. void __CDECL ipp_get_pentium_ident ( ippIntelCpuId* cpuid );
  87. int __CDECL ipp_is_GenuineIntel ( void );
  88. int __CDECL ipp_max_cpuid_input( void );
  89. int __CDECL ipp_get_cpuid( int regs[4], int valEAX, int valECX );
  90. void __CDECL ipp_get_cache_line_size( int* szCacheLine );
  91. int __CDECL ipp_isnan( double x );
  92. int __CDECL ipp_finite( double x );
  93. int __CDECL ipp_isnan_32f( float x );
  94. int __CDECL ipp_finite_32f( float x );
  95. #define ipp_isfinite ipp_finite
  96. unsigned int __CDECL ipp_control87 ( unsigned int newcw, unsigned int mask );
  97. unsigned int __CDECL ipp_status87 ( void );
  98. unsigned int __CDECL ipp_clear87 ( void );
  99. unsigned int __CDECL ipp_clear_ssx (void);
  100. /* topology/affinity */
  101. /* here are definitions of the CW bits exactly as x87 and ssx have */
  102. #define IPP_FPU_MASK_RC 0x0c00
  103. #define IPP_FPU_MASK_PC 0x0300
  104. #define IPP_FPU_MASK_RCPC 0x0f00
  105. #define IPP_FPU_RC_NEAR 0x0000
  106. #define IPP_FPU_RC_DOWN 0x0400
  107. #define IPP_FPU_RC_UP 0x0800
  108. #define IPP_FPU_RC_ZERO 0x0c00
  109. #define IPP_FPU_PC_24 0x0000
  110. #define IPP_FPU_PC_53 0x0200
  111. #define IPP_FPU_PC_64 0x0300
  112. unsigned int __CDECL ipp_set_rcpc_fpu( unsigned int newrcpc, unsigned int mask);
  113. void __CDECL ipp_set_cw_fpu( unsigned int cw );
  114. #define IPP_SSX_RC_NEAR 0x0000
  115. #define IPP_SSX_RC_DOWN 0x2000
  116. #define IPP_SSX_RC_UP 0x4000
  117. #define IPP_SSX_RC_ZERO 0x6000
  118. #define IPP_SSX_MASK_RC 0x6000
  119. unsigned int __CDECL ipp_set_rc_ssx( unsigned int newrc );
  120. void __CDECL ipp_set_cw_ssx( unsigned int cw );
  121. /* ================= FPU section ===================== */
  122. /* Control bits - disable exceptions */
  123. #define FPU_EXC_MSK 0x003f /* Exception Masks Mask */
  124. #define FPU_MSK_INVALID 0x0001 /* invalid operation */
  125. #define FPU_MSK_DENORMAL 0x0002 /* denormalized operand */
  126. #define FPU_MSK_ZERODIV 0x0004 /* zero divide */
  127. #define FPU_MSK_OVERFLOW 0x0008 /* overflow */
  128. #define FPU_MSK_UNDERFLOW 0x0010 /* underflow */
  129. #define FPU_MSK_INEXACT 0x0020 /* inexact (precision) */
  130. /* Status bits - exceptions */
  131. #define FPU_EXC_FLG 0x003f /* Exception Flags Mask */
  132. #define FPU_FLG_INVALID 0x0001 /* invalid operation */
  133. #define FPU_FLG_DENORMAL 0x0002 /* denormalized operand */
  134. #define FPU_FLG_ZERODIV 0x0004 /* zero divide */
  135. #define FPU_FLG_OVERFLOW 0x0008 /* overflow */
  136. #define FPU_FLG_UNDERFLOW 0x0010 /* underflow */
  137. #define FPU_FLG_INEXACT 0x0020 /* inexact (precision) */
  138. /* Control bits - rounding control */
  139. #define FPU_RND 0x0c00 /* Rounding Control Mask */
  140. #define FPU_RND_NEAR 0x0000 /* near */
  141. #define FPU_RND_DOWN 0x0400 /* down */
  142. #define FPU_RND_UP 0x0800 /* up */
  143. #define FPU_RND_CHOP 0x0c00 /* chop */
  144. /* Control bits - precision control */
  145. #define FPU_PRC 0x0300 /* Precision Control Mask */
  146. #define FPU_PRC_64 0x0300 /* 64 bits */
  147. #define FPU_PRC_53 0x0200 /* 53 bits */
  148. #define FPU_PRC_24 0x0000 /* 24 bits */
  149. /* Control bits - all masks */
  150. #define FPU_ALL 0x0f3f /* all masks */
  151. /* ============= definition for control/status world ============== */
  152. #define FPU_SET_EXC_MASK(mask) ps_set_cw_fpu(mask,FPU_EXC_MSK)
  153. #define FPU_GET_EXC_MASK() (ps_set_cw_fpu(0,0) & FPU_EXC_MSK)
  154. #define FPU_GET_EXC_FLAG() (ps_get_sw_fpu() & FPU_EXC_FLG)
  155. #define FPU_SET_RND_MODE(mode) ps_set_cw_fpu(mode,FPU_RND)
  156. #define FPU_GET_RND_MODE() (ps_set_cw_fpu(0,0) & FPU_RND)
  157. #define FPU_SET_PRC_MODE(mode) ps_set_cw_fpu(mode,FPU_PRC)
  158. #define FPU_GET_PRC_MODE() (ps_set_cw_fpu(0,0) & FPU_PRC)
  159. unsigned int __CDECL ps_set_cw_fpu( unsigned int newcw, unsigned int msk);
  160. unsigned int __CDECL ps_get_cw_fpu(void);
  161. unsigned int __CDECL ps_get_sw_fpu(void);
  162. unsigned int __CDECL ps_clear_fpu(void);
  163. /* ======================= SSX section ============================ */
  164. /* Control bits - disable exceptions */
  165. #define SSX_EXC_MSK 0x1f80 /* Disabling exception mask */
  166. #define SSX_MSK_INEXACT 0x1000 /* precision (inexact) */
  167. #define SSX_MSK_UNDERFLOW 0x0800 /* underflow */
  168. #define SSX_MSK_OVERFLOW 0x0400 /* overflow */
  169. #define SSX_MSK_ZERODIV 0x0200 /* divide by zero */
  170. #define SSX_MSK_DENORMAL 0x0100 /* denormalized */
  171. #define SSX_MSK_INVALID 0x0080 /* invalid operation */
  172. /* Status bits - exceptions */
  173. #define SSX_EXC_FLG 0x003f /* Exception flags mask */
  174. #define SSX_FLG_INEXACT 0x0020 /* precision (inexact) */
  175. #define SSX_FLG_UNDERFLOW 0x0010 /* underflow */
  176. #define SSX_FLG_OVERFLOW 0x0008 /* overflow */
  177. #define SSX_FLG_ZERODIV 0x0004 /* divide by zero */
  178. #define SSX_FLG_DENORMAL 0x0002 /* denormalized */
  179. #define SSX_FLG_INVALID 0x0001 /* invalid operation */
  180. /* Control bits - rounding control */
  181. #define SSX_RND 0x6000 /* Rounding control mask */
  182. #define SSX_RND_NEAR 0x0000 /* near */
  183. #define SSX_RND_DOWN 0x2000 /* down */
  184. #define SSX_RND_UP 0x4000 /* up */
  185. #define SSX_RND_CHOP 0x6000 /* chop */
  186. /* Control bits - flush to zero mode */
  187. #define SSX_FZ 0x8000 /* Flush to zero mask */
  188. #define SSX_FZ_ENABLE 0x8000 /* flush to zero */
  189. #define SSX_FZ_DISABLE 0x0000 /* not flush to zero */
  190. /* Control bits - denormals are zero mode */
  191. #define SSX_DAZ 0x0040 /* denorm. are zero mask */
  192. #define SSX_DAZ_ENABLE 0x0040 /* denorm. are zero */
  193. #define SSX_DAZ_DISABLE 0x0000 /* denorm. are not zero */
  194. #define SSX_ALL 0xffbf /* All masks */
  195. /* ==================== definition for SSX register =============== */
  196. #define SSX_SET_EXC_MASK(mask) ps_set_ssx(mask,SSX_EXC_MSK)
  197. #define SSX_GET_EXC_MASK() (ps_get_ssx() & SSX_EXC_MSK)
  198. #define SSX_SET_EXC_FLAG(flag) ps_set_ssx(flag,SSX_EXC_FLG)
  199. #define SSX_GET_EXC_FLAG() (ps_get_ssx() & SSX_EXC_FLG)
  200. #define SSX_SET_RND_MODE(mode) ps_set_ssx(mode,SSX_RND)
  201. #define SSX_GET_RND_MODE() (ps_get_ssx() & SSX_RND)
  202. #define SSX_SET_FZ_MODE(mode) ps_set_ssx(mode,SSX_FZ)
  203. #define SSX_GET_FZ_MODE() (ps_get_ssx() & SSX_FZ)
  204. #define SSX_SET_DAZ_MODE(mode) ps_set_ssx(mode,SSX_DAZ)
  205. #define SSX_GET_DAZ_MODE() (ps_get_ssx() & SSX_DAZ)
  206. unsigned int __CDECL ps_set_ssx(unsigned int newssx, unsigned int msk);
  207. unsigned int __CDECL ps_get_ssx(void);
  208. unsigned int __CDECL ipp_tst_daz_ssx(void);
  209. #if defined( __cplusplus )
  210. }
  211. #endif
  212. #endif /* __CPUDEF_H__ */
  213. /* ////////////////////////// End of file "cpudef.h" //////////////////////// */