enclave_creator_hw.cpp 12 KB

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  1. /*
  2. * Copyright (C) 2011-2018 Intel Corporation. All rights reserved.
  3. *
  4. * Redistribution and use in source and binary forms, with or without
  5. * modification, are permitted provided that the following conditions
  6. * are met:
  7. *
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in
  12. * the documentation and/or other materials provided with the
  13. * distribution.
  14. * * Neither the name of Intel Corporation nor the names of its
  15. * contributors may be used to endorse or promote products derived
  16. * from this software without specific prior written permission.
  17. *
  18. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  28. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29. *
  30. */
  31. #include "enclave.h"
  32. #include "enclave_creator_hw.h"
  33. #include "se_trace.h"
  34. #include "se_page_attr.h"
  35. #include "isgx_user.h"
  36. #include "sig_handler.h"
  37. #include "se_error_internal.h"
  38. #include "se_memcpy.h"
  39. #include "se_atomic.h"
  40. #include "se_detect.h"
  41. #include "cpuid.h"
  42. #include "rts.h"
  43. #include <assert.h>
  44. #include <sys/types.h>
  45. #include <sys/stat.h>
  46. #include <fcntl.h>
  47. #include <sys/ioctl.h>
  48. #include <errno.h>
  49. #include <sys/mman.h>
  50. #include <stdlib.h>
  51. #define POINTER_TO_U64(A) ((__u64)((uintptr_t)(A)))
  52. #define SGX_CPUID 0x12
  53. static EnclaveCreatorHW g_enclave_creator_hw;
  54. EnclaveCreator* g_enclave_creator = &g_enclave_creator_hw;
  55. static uint64_t g_eid = 0x1;
  56. EnclaveCreatorHW::EnclaveCreatorHW():
  57. m_hdevice(-1),
  58. m_sig_registered(false),
  59. m_in_kernel_driver(false)
  60. {
  61. se_mutex_init(&m_sig_mutex);
  62. }
  63. EnclaveCreatorHW::~EnclaveCreatorHW()
  64. {
  65. close_se_device();
  66. }
  67. int EnclaveCreatorHW::error_driver2urts(int driver_error)
  68. {
  69. int ret = SGX_ERROR_UNEXPECTED;
  70. switch(driver_error)
  71. {
  72. case SGX_INVALID_ATTRIBUTE:
  73. ret = SGX_ERROR_INVALID_ATTRIBUTE;
  74. break;
  75. case SGX_INVALID_MEASUREMENT:
  76. ret = SE_ERROR_INVALID_MEASUREMENT;
  77. break;
  78. case SGX_INVALID_SIG_STRUCT:
  79. case SGX_INVALID_SIGNATURE:
  80. ret = SGX_ERROR_INVALID_SIGNATURE;
  81. break;
  82. case SGX_INVALID_LICENSE:
  83. ret = SE_ERROR_INVALID_LAUNCH_TOKEN;
  84. break;
  85. case SGX_INVALID_CPUSVN:
  86. ret = SGX_ERROR_INVALID_CPUSVN;
  87. break;
  88. case SGX_INVALID_ISVSVN:
  89. ret = SGX_ERROR_INVALID_ISVSVN;
  90. break;
  91. case SGX_UNMASKED_EVENT:
  92. ret = SGX_ERROR_DEVICE_BUSY;
  93. break;
  94. case (int)SGX_POWER_LOST_ENCLAVE: // [-Wc++11-narrowing]
  95. ret = SGX_ERROR_ENCLAVE_LOST;
  96. break;
  97. case (int)SGX_LE_ROLLBACK:
  98. ret = SE_ERROR_INVALID_ISVSVNLE;
  99. break;
  100. default:
  101. SE_TRACE(SE_TRACE_WARNING, "unexpected error %#x from driver, should be uRTS/driver bug\n", driver_error);
  102. ret = SGX_ERROR_UNEXPECTED;
  103. break;
  104. }
  105. return ret;
  106. }
  107. int EnclaveCreatorHW::create_enclave(secs_t *secs, sgx_enclave_id_t *enclave_id, void **start_addr, bool ae)
  108. {
  109. assert(secs != NULL && enclave_id != NULL && start_addr != NULL);
  110. UNUSED(ae);
  111. if (false == open_se_device())
  112. return SGX_ERROR_NO_DEVICE;
  113. SE_TRACE(SE_TRACE_DEBUG, "\n secs.attibutes.flags = %llx, secs.attributes.xfrm = %llx \n"
  114. , secs->attributes.flags, secs->attributes.xfrm);
  115. //SECS:BASEADDR must be naturally aligned on an SECS.SIZE boundary
  116. //This alignment is guaranteed by driver
  117. void* enclave_base = mmap(NULL, (size_t)secs->size, PROT_NONE, MAP_SHARED, m_hdevice, 0);
  118. if(enclave_base == MAP_FAILED)
  119. {
  120. SE_TRACE(SE_TRACE_WARNING, "\ncreate enclave: mmap failed, errno = %d\n", errno);
  121. return SGX_ERROR_OUT_OF_MEMORY;
  122. }
  123. secs->base = enclave_base;
  124. struct sgx_enclave_create param = {0};
  125. param.src = POINTER_TO_U64(secs);
  126. int ret = ioctl(m_hdevice, SGX_IOC_ENCLAVE_CREATE, &param);
  127. if(ret)
  128. {
  129. SE_TRACE(SE_TRACE_WARNING, "\nSGX_IOC_ENCLAVE_CREATE failed: errno = %d\n", errno);
  130. return error_driver2urts(ret);
  131. }
  132. *enclave_id = se_atomic_inc64(&g_eid);
  133. *start_addr = secs->base;
  134. return SGX_SUCCESS;
  135. }
  136. int EnclaveCreatorHW::add_enclave_page(sgx_enclave_id_t enclave_id, void *src, uint64_t rva, const sec_info_t &sinfo, uint32_t attr)
  137. {
  138. assert((rva & ((1<<SE_PAGE_SHIFT)-1)) == 0);
  139. void* source = src;
  140. uint8_t color_page[SE_PAGE_SIZE] = { 0 };
  141. if(NULL == source)
  142. {
  143. memset(color_page, 0, SE_PAGE_SIZE);
  144. source = reinterpret_cast<void*>(&color_page);
  145. }
  146. int ret = 0;
  147. struct sgx_enclave_add_page addp = { 0, 0, 0, 0 };
  148. addp.addr = enclave_id + rva;
  149. addp.src = POINTER_TO_U64(source);
  150. addp.secinfo = POINTER_TO_U64(const_cast<sec_info_t*>(&sinfo));
  151. if(((1<<DoEEXTEND) & attr))
  152. addp.mrmask |= 0xFFFF;
  153. ret = ioctl(m_hdevice, SGX_IOC_ENCLAVE_ADD_PAGE, &addp);
  154. if(ret) {
  155. SE_TRACE(SE_TRACE_WARNING, "\nAdd Page - %p to %p... FAIL\n", source, rva);
  156. return error_driver2urts(ret);
  157. }
  158. return SGX_SUCCESS;
  159. }
  160. int EnclaveCreatorHW::try_init_enclave(sgx_enclave_id_t enclave_id, enclave_css_t *enclave_css, token_t *launch)
  161. {
  162. int ret = 0;
  163. if (m_in_kernel_driver == false)
  164. {
  165. struct sgx_enclave_init initp = { 0, 0, 0 };
  166. initp.addr = enclave_id;
  167. initp.sigstruct = POINTER_TO_U64(enclave_css);
  168. //license should NOT be NULL, because it has been checked in urts_com.h::_create_enclave(...)
  169. assert(launch != NULL);
  170. initp.einittoken = POINTER_TO_U64(launch);
  171. ret = ioctl(m_hdevice, SGX_IOC_ENCLAVE_INIT, &initp);
  172. }
  173. else
  174. {
  175. struct sgx_enclave_init_in_kernel initp = { 0, 0 };
  176. initp.addr = enclave_id;
  177. initp.sigstruct = POINTER_TO_U64(enclave_css);
  178. ret = ioctl(m_hdevice, SGX_IOC_ENCLAVE_INIT_IN_KERNEL, &initp);
  179. }
  180. if (ret) {
  181. SE_TRACE(SE_TRACE_WARNING, "\nSGX_IOC_ENCLAVE_INIT failed error = %d\n", ret);
  182. return error_driver2urts(ret);
  183. }
  184. //register signal handler
  185. se_mutex_lock(&m_sig_mutex);
  186. if(false == m_sig_registered)
  187. {
  188. reg_sig_handler();
  189. m_sig_registered = true;
  190. }
  191. se_mutex_unlock(&m_sig_mutex);
  192. return SGX_SUCCESS;
  193. }
  194. int EnclaveCreatorHW::destroy_enclave(sgx_enclave_id_t enclave_id, uint64_t enclave_size)
  195. {
  196. int ret = SGX_SUCCESS;
  197. ret = munmap((void*)enclave_id, (size_t)enclave_size);
  198. if (0 != ret) {
  199. SE_TRACE(SE_TRACE_WARNING, "destroy SGX enclave failed, error = %d\n", errno);
  200. ret = SGX_ERROR_UNEXPECTED;
  201. }
  202. return ret;
  203. }
  204. bool EnclaveCreatorHW::get_plat_cap(sgx_misc_attribute_t *misc_attr)
  205. {
  206. // need to update code to support HyperV ECO
  207. return get_plat_cap_by_cpuid(misc_attr);
  208. }
  209. bool EnclaveCreatorHW::open_se_device()
  210. {
  211. LockGuard lock(&m_dev_mutex);
  212. int fd = -1;
  213. if(-1 != m_hdevice)
  214. {
  215. return true;
  216. }
  217. fd = open("/dev/isgx", O_RDWR);
  218. if (-1 == fd) {
  219. fd = open("/dev/sgx", O_RDWR);
  220. if (-1 == fd) {
  221. SE_TRACE(SE_TRACE_WARNING, "Failed to open Intel SGX device\n");
  222. return false;
  223. }
  224. m_in_kernel_driver = true;
  225. }
  226. m_hdevice = fd;
  227. return true;
  228. }
  229. void EnclaveCreatorHW::close_se_device()
  230. {
  231. LockGuard lock(&m_dev_mutex);
  232. if (m_hdevice != -1)
  233. {
  234. close(m_hdevice);
  235. m_hdevice = -1;
  236. }
  237. }
  238. int EnclaveCreatorHW::emodpr(uint64_t addr, uint64_t size, uint64_t flag)
  239. {
  240. sgx_modification_param params;
  241. memset(&params, 0 ,sizeof(sgx_modification_param));
  242. params.range.start_addr = (unsigned long)addr;
  243. params.range.nr_pages = (unsigned int)(size/SE_PAGE_SIZE);
  244. params.flags = (unsigned long)flag;
  245. int ret = ioctl(m_hdevice, SGX_IOC_ENCLAVE_EMODPR, &params);
  246. if (ret)
  247. {
  248. SE_TRACE(SE_TRACE_ERROR, "SGX_IOC_ENCLAVE_EMODPR failed %d\n", errno);
  249. return error_driver2urts(ret);
  250. }
  251. return SGX_SUCCESS;
  252. }
  253. int EnclaveCreatorHW::mktcs(uint64_t tcs_addr)
  254. {
  255. sgx_range params;
  256. memset(&params, 0 ,sizeof(sgx_range));
  257. params.start_addr = (unsigned long)tcs_addr;
  258. params.nr_pages = 1;
  259. int ret = ioctl(m_hdevice, SGX_IOC_ENCLAVE_MKTCS, &params);
  260. if (ret)
  261. {
  262. SE_TRACE(SE_TRACE_ERROR, "MODIFY_TYPE failed %d\n", errno);
  263. return error_driver2urts(ret);
  264. }
  265. return SGX_SUCCESS;
  266. }
  267. int EnclaveCreatorHW::trim_range(uint64_t fromaddr, uint64_t toaddr)
  268. {
  269. sgx_range params;
  270. memset(&params, 0 ,sizeof(sgx_range));
  271. params.start_addr = (unsigned long)fromaddr;
  272. params.nr_pages = (unsigned int)((toaddr - fromaddr)/SE_PAGE_SIZE);
  273. int ret= ioctl(m_hdevice, SGX_IOC_ENCLAVE_TRIM, &params);
  274. if (ret)
  275. {
  276. SE_TRACE(SE_TRACE_ERROR, "SGX_IOC_ENCLAVE_TRIM failed %d\n", errno);
  277. return error_driver2urts(ret);
  278. }
  279. return SGX_SUCCESS;
  280. }
  281. int EnclaveCreatorHW::trim_accept(uint64_t addr)
  282. {
  283. sgx_range params;
  284. memset(&params, 0 ,sizeof(sgx_range));
  285. params.start_addr = (unsigned long)addr;
  286. params.nr_pages = 1;
  287. int ret = ioctl(m_hdevice, SGX_IOC_ENCLAVE_NOTIFY_ACCEPT, &params);
  288. if (ret)
  289. {
  290. SE_TRACE(SE_TRACE_ERROR, "TRIM_RANGE_COMMIT failed %d\n", errno);
  291. return error_driver2urts(ret);
  292. }
  293. return SGX_SUCCESS;
  294. }
  295. int EnclaveCreatorHW::remove_range(uint64_t fromaddr, uint64_t numpages)
  296. {
  297. int ret = -1;
  298. uint64_t i;
  299. unsigned long start;
  300. for (i = 0; i < numpages; i++)
  301. {
  302. start = (unsigned long)fromaddr + (unsigned long)(i << SE_PAGE_SHIFT);
  303. ret = ioctl(m_hdevice, SGX_IOC_ENCLAVE_PAGE_REMOVE, &start);
  304. if (ret)
  305. {
  306. SE_TRACE(SE_TRACE_ERROR, "PAGE_REMOVE failed %d\n", errno);
  307. return error_driver2urts(ret);
  308. }
  309. }
  310. return SGX_SUCCESS;
  311. }
  312. //EDMM is supported if and only if all of the following requirements are met:
  313. //1. We operate in HW mode
  314. //2. CPU has EDMM support
  315. //3. Driver has EDMM support
  316. //4. Both the uRTS version and enclave (metadata) version are higher than 1.5
  317. bool EnclaveCreatorHW::is_EDMM_supported(sgx_enclave_id_t enclave_id)
  318. {
  319. bool supported = false, driver_supported = false, cpu_edmm = false;
  320. CEnclave *enclave = CEnclavePool::instance()->get_enclave(enclave_id);
  321. if (enclave == NULL)
  322. return false;
  323. cpu_edmm = is_cpu_edmm();
  324. driver_supported = is_driver_compatible();
  325. //return value of get_enclave_version() considers the version of uRTS and enclave metadata
  326. supported = use_se_hw() && cpu_edmm && driver_supported && (enclave->get_enclave_version() >= SDK_VERSION_2_0);
  327. return supported;
  328. }
  329. bool EnclaveCreatorHW::is_cpu_edmm() const
  330. {
  331. bool cpu_edmm = false;
  332. int a[4] = {0,0,0,0};
  333. //Check CPU EDMM capability by CPUID
  334. __cpuid(a, 0);
  335. if (a[0] < SGX_CPUID)
  336. return false;
  337. __cpuidex(a, SGX_CPUID, 0);
  338. if (!(a[0] & 1))
  339. return false;
  340. cpu_edmm = (a[0] & 2) != 0;
  341. return cpu_edmm;
  342. }
  343. bool EnclaveCreatorHW::is_driver_compatible()
  344. {
  345. static bool ret = driver_support_edmm();
  346. return ret;
  347. }
  348. bool EnclaveCreatorHW::is_in_kernel_driver()
  349. {
  350. open_se_device();
  351. return m_in_kernel_driver;
  352. }
  353. bool EnclaveCreatorHW::driver_support_edmm()
  354. {
  355. int ret;
  356. sgx_modification_param p;
  357. p.flags = 0;
  358. p.range.start_addr = 0;
  359. p.range.nr_pages = 0;
  360. if (false == open_se_device())
  361. {
  362. return false;
  363. }
  364. ret = ioctl(m_hdevice, SGX_IOC_ENCLAVE_EMODPR, &p);
  365. if ((ret == -1) && (errno == ENOTTY))
  366. {
  367. return false;
  368. }
  369. else
  370. {
  371. return true;
  372. }
  373. }