cpu_features.cpp 5.8 KB

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  1. /*
  2. * Copyright (C) 2011-2017 Intel Corporation. All rights reserved.
  3. *
  4. * Redistribution and use in source and binary forms, with or without
  5. * modification, are permitted provided that the following conditions
  6. * are met:
  7. *
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in
  12. * the documentation and/or other materials provided with the
  13. * distribution.
  14. * * Neither the name of Intel Corporation nor the names of its
  15. * contributors may be used to endorse or promote products derived
  16. * from this software without specific prior written permission.
  17. *
  18. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  28. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29. *
  30. */
  31. #include "se_cpu_feature_defs.h"
  32. #include "se_types.h"
  33. #include "cpu_features.h"
  34. void get_cpu_features(uint64_t *__intel_cpu_feature_indicator)
  35. {
  36. unsigned int cpuid0_eax, cpuid0_ebx, cpuid0_ecx, cpuid0_edx;
  37. unsigned int cpuid1_eax, cpuid1_ebx, cpuid1_ecx, cpuid1_edx;
  38. unsigned int cpuid7_eax, cpuid7_ebx, cpuid7_ecx, cpuid7_edx;
  39. unsigned int ecpuid1_eax, ecpuid1_ebx, ecpuid1_ecx, ecpuid1_edx;
  40. uint64_t cpu_feature_indicator = CPU_FEATURE_GENERIC_IA32;
  41. sgx_cpuid(0, &cpuid0_eax, &cpuid0_ebx, &cpuid0_ecx, &cpuid0_edx);
  42. if(cpuid0_eax == 0 ||
  43. !(cpuid0_ebx == CPU_GENU_VAL &&
  44. cpuid0_edx == CPU_INEI_VAL &&
  45. cpuid0_ecx == CPU_NTEL_VAL))
  46. {
  47. *__intel_cpu_feature_indicator = cpu_feature_indicator;
  48. return;
  49. }
  50. sgx_cpuid(1, &cpuid1_eax, &cpuid1_ebx, &cpuid1_ecx, &cpuid1_edx);
  51. if (CPU_MODEL(cpuid1_eax) == CPU_ATOM1 ||
  52. CPU_MODEL(cpuid1_eax) == CPU_ATOM2 ||
  53. CPU_MODEL(cpuid1_eax) == CPU_ATOM3) {
  54. cpu_feature_indicator |= CPU_FEATURE_FULL_INORDER;
  55. }
  56. // Walk through supported features
  57. if (CPU_HAS_FPU(cpuid1_edx)) {
  58. cpu_feature_indicator |= CPU_FEATURE_FPU;
  59. }
  60. if (CPU_HAS_CMOV(cpuid1_edx)) {
  61. cpu_feature_indicator |= CPU_FEATURE_CMOV;
  62. }
  63. if (CPU_HAS_MMX(cpuid1_edx)) {
  64. cpu_feature_indicator |= CPU_FEATURE_MMX;
  65. }
  66. if (CPU_HAS_FXSAVE(cpuid1_edx)) {
  67. cpu_feature_indicator |= CPU_FEATURE_FXSAVE;
  68. if (CPU_HAS_SSE(cpuid1_edx)) {
  69. cpu_feature_indicator |= CPU_FEATURE_SSE;
  70. }
  71. if (CPU_HAS_SSE2(cpuid1_edx)) {
  72. cpu_feature_indicator |= CPU_FEATURE_SSE2;
  73. }
  74. if (CPU_HAS_SSE3(cpuid1_ecx)) {
  75. cpu_feature_indicator |= CPU_FEATURE_SSE3;
  76. }
  77. if (CPU_HAS_SSSE3(cpuid1_ecx)) {
  78. cpu_feature_indicator |= CPU_FEATURE_SSSE3;
  79. }
  80. if (CPU_HAS_MOVBE(cpuid1_ecx)) {
  81. cpu_feature_indicator |= CPU_FEATURE_MOVBE;
  82. }
  83. //
  84. // Penryn is a P6 with SNI support.
  85. //
  86. if (CPU_HAS_SSE4_1(cpuid1_ecx)) {
  87. cpu_feature_indicator |= CPU_FEATURE_SSE4_1;
  88. }
  89. if (CPU_HAS_SSE4_2(cpuid1_ecx)) {
  90. cpu_feature_indicator |= CPU_FEATURE_SSE4_2;
  91. }
  92. if (CPU_HAS_POPCNT(cpuid1_ecx)) {
  93. cpu_feature_indicator |= CPU_FEATURE_POPCNT;
  94. }
  95. if (CPU_HAS_PCLMULQDQ(cpuid1_ecx)) {
  96. cpu_feature_indicator |= CPU_FEATURE_PCLMULQDQ;
  97. }
  98. if (CPU_HAS_AES(cpuid1_ecx)) {
  99. cpu_feature_indicator |= CPU_FEATURE_AES;
  100. }
  101. }
  102. // IvyBridge
  103. if (CPU_HAS_RDRAND(cpuid1_ecx)) {
  104. cpu_feature_indicator |= CPU_FEATURE_RDRND;
  105. }
  106. sgx_cpuidex(7, 0, &cpuid7_eax, &cpuid7_ebx, &cpuid7_ecx, &cpuid7_edx);
  107. sgx_cpuid(0x80000001, &ecpuid1_eax, &ecpuid1_ebx, &ecpuid1_ecx, &ecpuid1_edx);
  108. // Haswell
  109. // BMI checks for both ebx[3] and ebx[8] (VEX-encoded instructions)
  110. if (CPU_HAS_BMI(cpuid7_ebx)) {
  111. cpu_feature_indicator |= CPU_FEATURE_BMI;
  112. }
  113. if (CPU_HAS_LZCNT(ecpuid1_ecx)) {
  114. cpu_feature_indicator |= CPU_FEATURE_LZCNT;
  115. }
  116. if (CPU_HAS_PREFETCHW(ecpuid1_ecx)) {
  117. cpu_feature_indicator |= CPU_FEATURE_PREFETCHW;
  118. }
  119. if (CPU_HAS_HLE(cpuid7_ebx)) {
  120. cpu_feature_indicator |= CPU_FEATURE_HLE;
  121. }
  122. if (CPU_HAS_RTM(cpuid7_ebx)) {
  123. cpu_feature_indicator |= CPU_FEATURE_RTM;
  124. }
  125. if (CPU_HAS_RDSEED(cpuid7_ebx)) {
  126. cpu_feature_indicator |= CPU_FEATURE_RDSEED;
  127. }
  128. if (CPU_HAS_ADCOX(cpuid7_ebx)) {
  129. cpu_feature_indicator |= CPU_FEATURE_ADCOX;
  130. }
  131. if (CPU_HAS_XSAVE(cpuid1_ecx))
  132. {
  133. //don't get xcr0_features, tRTS will do it.
  134. if (CPU_HAS_AVX(cpuid1_ecx)) {
  135. cpu_feature_indicator |= CPU_FEATURE_AVX;
  136. }
  137. // IvyBridge
  138. if (CPU_HAS_F16C(cpuid1_ecx)) {
  139. cpu_feature_indicator |= CPU_FEATURE_F16C;
  140. }
  141. // Haswell
  142. if (CPU_HAS_AVX2(cpuid7_ebx)) {
  143. cpu_feature_indicator |= CPU_FEATURE_AVX2;
  144. }
  145. if (CPU_HAS_FMA(cpuid1_ecx)) {
  146. cpu_feature_indicator |= CPU_FEATURE_FMA;
  147. }
  148. }
  149. *__intel_cpu_feature_indicator = cpu_feature_indicator;
  150. }