se_cpu_feature_defs.h 9.7 KB

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  1. /*
  2. * Copyright (C) 2011-2017 Intel Corporation. All rights reserved.
  3. *
  4. * Redistribution and use in source and binary forms, with or without
  5. * modification, are permitted provided that the following conditions
  6. * are met:
  7. *
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in
  12. * the documentation and/or other materials provided with the
  13. * distribution.
  14. * * Neither the name of Intel Corporation nor the names of its
  15. * contributors may be used to endorse or promote products derived
  16. * from this software without specific prior written permission.
  17. *
  18. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  28. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29. *
  30. */
  31. #ifndef _SE_CPU_FEATURE_DEFS_H_
  32. #define _SE_CPU_FEATURE_DEFS_H_
  33. /*
  34. * Different extended model + model values for Silverthorn.
  35. */
  36. #define CPU_ATOM1 0x1c
  37. #define CPU_ATOM2 0x26
  38. #define CPU_ATOM3 0x27
  39. /*
  40. * The processor family is an 8-bit value obtained by adding the
  41. * Extended Family field of the processor signature returned by
  42. * CPUID Function 1 with the Family field.
  43. * F = (CPUID(1).EAX[27:20] >> 20) + (CPUID(1).EAX[11:8] >> 8)
  44. */
  45. #define CPU_FAMILY(x) (((((x) >> 20) & 0xffU) | (((x) >> 8) & 0xfU)) & 0xffU)
  46. /* The processor model is an 8-bit value obtained by shifting left 4
  47. * the Extended Model field of the processor signature returned by
  48. * CPUID Function 1 then adding the Model field.
  49. * M = (CPUID(1).EAX[19:16] >> 12) + (CPUID(1).EAX[7:4] >> 4)
  50. */
  51. #define CPU_MODEL(x) ((((x) >> 12) & 0xf0U) | (((x) >> 4) & 0xfU))
  52. #define CPU_STEPPING(x) (((x) >> 0) & 0xf)
  53. #define CPU_HAS_MMX(x) (((x) & (1 << 23)) != 0)
  54. #define CPU_HAS_FXSAVE(x) (((x) & (1 << 24)) != 0)
  55. #define CPU_HAS_SSE(x) (((x) & (1 << 25)) != 0)
  56. #define CPU_HAS_SSE2(x) (((x) & (1 << 26)) != 0)
  57. #define CPU_HAS_PNI(x) (((x) & (1 << 0)) != 0)
  58. #define CPU_HAS_MNI(x) (((x) & (1 << 9)) != 0)
  59. #define CPU_HAS_SNI(x) (((x) & (1 << 19)) != 0)
  60. #define CPU_HAS_MOVBE(x) (((x) & (1 << 22)) != 0)
  61. #define CPU_HAS_SSE4_2(x) (((x) & (1 << 20)) != 0)
  62. #define CPU_HAS_POPCNT(x) (((x) & (1 << 23)) != 0)
  63. #define CPU_HAS_PCLMULQDQ(x) (((x) & (1 << 1)) != 0)
  64. #define CPU_HAS_AES(x) (((x) & (1 << 25)) != 0)
  65. #define CPU_HAS_XSAVE(x) (((x) & (1 << 27)) != 0)
  66. #define CPU_HAS_AVX(x) (((x) & (1 << 28)) != 0)
  67. #define XFEATURE_ENABLED_AVX(x) \
  68. (((x) & 0x06) == 0x06)
  69. #define CPU_HAS_F16C(x) (((x) & (1 << 29)) != 0)
  70. #define CPU_HAS_RDRAND(x) (((x) & (1 << 30)) != 0)
  71. #define CPU_HAS_IVB(x) (CPU_HAS_F16C(x) && CPU_HAS_RDRAND(x))
  72. #define CPU_HAS_IVB_NORDRAND(x) (CPU_HAS_F16C(x))
  73. #define CPU_HAS_AVX2(x) (((x) & (1 << 5)) != 0)
  74. #define CPU_HAS_HLE(x) (((x) & (1 << 4)) != 0)
  75. #define CPU_HAS_RTM(x) (((x) & (1 << 11)) != 0)
  76. #define CPU_HAS_ADCOX(x) (((x) & (1 << 19)) != 0)
  77. #define CPU_HAS_RDSEED(x) (((x) & (1 << 18)) != 0)
  78. #define CPU_HAS_BMI(x) (((x) & (1 << 3)) != 0 && \
  79. ((x) & (1 << 8)) != 0)
  80. #define CPU_HAS_LZCNT(x) (((x) & (1 << 5)) != 0)
  81. #define CPU_HAS_PREFETCHW(x) (((x) & (1 << 8)) != 0)
  82. #define CPU_HAS_FMA(x) (((x) & (1 << 12)) != 0)
  83. #define CPU_HAS_HSW(cpuid7_ebx, ecpuid1_ecx, cpuid1_ecx) \
  84. (CPU_HAS_AVX2(cpuid7_ebx) && CPU_HAS_BMI(cpuid7_ebx) && \
  85. CPU_HAS_LZCNT(ecpuid1_ecx) && CPU_HAS_FMA(cpuid1_ecx) && \
  86. CPU_HAS_HLE(cpuid7_ebx) && CPU_HAS_RTM(cpuid7_ebx))
  87. #define CPU_HAS_FPU(x) (((x) & (1 << 0)) != 0)
  88. #define CPU_HAS_CMOV(x) (((x) & (1 << 15)) != 0)
  89. #define CPU_HAS_SSE3(x) (((x) & (1 << 0)) != 0)
  90. #define CPU_HAS_SSSE3(x) (((x) & (1 << 9)) != 0)
  91. #define CPU_HAS_SSE4_1(x) (((x) & (1 << 19)) != 0)
  92. #define CPU_HAS_LRBNI(x) (((x) & (1 << 1)) != 0)
  93. #define CPU_HAS_LRB2(x) (((x) & (1 << 4)) != 0)
  94. #define CPU_GENU_VAL ('G' << 0 | 'e' << 8 | 'n' << 16 | 'u' << 24)
  95. #define CPU_INEI_VAL ('i' << 0 | 'n' << 8 | 'e' << 16 | 'I' << 24)
  96. #define CPU_NTEL_VAL ('n' << 0 | 't' << 8 | 'e' << 16 | 'l' << 24)
  97. /*
  98. * These values must be in sync with dev/proton/globals/glob_cpu_info.c
  99. * c_legacy_cpu_set_xxx constants.
  100. */
  101. #define CPU_GENERIC 0x1
  102. #define CPU_PENTIUM 0x2
  103. #define CPU_PENTIUM_PRO 0x4
  104. #define CPU_PENTIUM_MMX 0x8
  105. #define CPU_PENTIUM_II 0x10
  106. #define CPU_PENTIUM_II_FXSV 0x20
  107. #define CPU_PENTIUM_III 0x40
  108. #define CPU_PENTIUM_III_SSE 0x80
  109. #define CPU_PENTIUM_4 0x100
  110. #define CPU_PENTIUM_4_SSE2 0x200
  111. #define CPU_BNI 0x400
  112. #define CPU_PENTIUM_4_PNI 0x800
  113. #define CPU_MNI 0x1000
  114. #define CPU_SNI 0x2000
  115. #define CPU_BNL 0x4000
  116. #define CPU_NHM 0x8000
  117. #define CPU_WSM 0x10000
  118. #define CPU_SNB 0x20000
  119. #define CPU_IVB 0x40000
  120. #define CPU_HSW 0x400000
  121. #define CPU_PENTIUM_FAMILY 5
  122. #define CPU_PPRO_FAMILY 6
  123. #define CPU_WMT_FAMILY 15
  124. /*
  125. * The processor is a generic IA32 CPU
  126. */
  127. #define CPU_FEATURE_GENERIC_IA32 0x00000001ULL
  128. /*
  129. * Floating point unit is on-chip.
  130. */
  131. #define CPU_FEATURE_FPU 0x00000002ULL
  132. /*
  133. * Conditional mov instructions are supported.
  134. */
  135. #define CPU_FEATURE_CMOV 0x00000004ULL
  136. /*
  137. * The processor supports the MMX technology instruction set extensions
  138. * to Intel Architecture.
  139. */
  140. #define CPU_FEATURE_MMX 0x00000008ULL
  141. /*
  142. * The FXSAVE and FXRSTOR instructions are supported for fast
  143. * save and restore of the floating point context.
  144. */
  145. #define CPU_FEATURE_FXSAVE 0x00000010ULL
  146. /*
  147. * Indicates the processor supports the Streaming SIMD Extensions Instructions.
  148. */
  149. #define CPU_FEATURE_SSE 0x00000020ULL
  150. /*
  151. * Indicates the processor supports the Streaming SIMD
  152. * Extensions 2 Instructions.
  153. */
  154. #define CPU_FEATURE_SSE2 0x00000040ULL
  155. /*
  156. * Indicates the processor supports the Streaming SIMD
  157. * Extensions 3 Instructions. (PNI)
  158. */
  159. #define CPU_FEATURE_SSE3 0x00000080ULL
  160. /*
  161. * The processor supports the Supplemental Streaming SIMD Extensions 3
  162. * instructions. (MNI)
  163. */
  164. #define CPU_FEATURE_SSSE3 0x00000100ULL
  165. /*
  166. * The processor supports the Streaming SIMD Extensions 4.1 instructions.(SNI)
  167. */
  168. #define CPU_FEATURE_SSE4_1 0x00000200ULL
  169. /*
  170. * The processor supports the Streaming SIMD Extensions 4.1 instructions.
  171. * (NNI + STTNI)
  172. */
  173. #define CPU_FEATURE_SSE4_2 0x00000400ULL
  174. /*
  175. * The processor supports POPCNT instruction.
  176. */
  177. #define CPU_FEATURE_POPCNT 0x00000800ULL
  178. /*
  179. * The processor supports MOVBE instruction.
  180. */
  181. #define CPU_FEATURE_MOVBE 0x00001000ULL
  182. /*
  183. * The processor supports PCLMULQDQ instruction.
  184. */
  185. #define CPU_FEATURE_PCLMULQDQ 0x00002000ULL
  186. /*
  187. * The processor supports instruction extension for encryption.
  188. */
  189. #define CPU_FEATURE_AES 0x00004000ULL
  190. /*
  191. * The processor supports 16-bit floating-point conversions instructions.
  192. */
  193. #define CPU_FEATURE_F16C 0x00008000ULL
  194. /*
  195. * The processor supports AVX instruction extension.
  196. */
  197. #define CPU_FEATURE_AVX 0x00010000ULL
  198. /*
  199. * The processor supports RDRND (read random value) instruction.
  200. */
  201. #define CPU_FEATURE_RDRND 0x00020000ULL
  202. /*
  203. * The processor supports FMA instructions.
  204. */
  205. #define CPU_FEATURE_FMA 0x00040000ULL
  206. /*
  207. * The processor supports two groups of advanced bit manipulation extensions. - Haswell introduced, AVX2 related
  208. */
  209. #define CPU_FEATURE_BMI 0x00080000ULL
  210. /*
  211. * The processor supports LZCNT instruction (counts the number of leading zero
  212. * bits). - Haswell introduced
  213. */
  214. #define CPU_FEATURE_LZCNT 0x00100000ULL
  215. /*
  216. * The processor supports HLE extension (hardware lock elision). - Haswell introduced
  217. */
  218. #define CPU_FEATURE_HLE 0x00200000ULL
  219. /*
  220. * The processor supports RTM extension (restricted transactional memory) - Haswell AVX2 related.
  221. */
  222. #define CPU_FEATURE_RTM 0x00400000ULL
  223. /*
  224. * The processor supports AVX2 instruction extension.
  225. */
  226. #define CPU_FEATURE_AVX2 0x00800000ULL
  227. /*
  228. * The processor supports AVX512 instruction extension.
  229. */
  230. #define CPU_FEATURE_AVX512 0x01000000ULL
  231. /*
  232. * The processor supports the PREFETCHW instruction.
  233. */
  234. #define CPU_FEATURE_PREFETCHW 0x02000000ULL
  235. /*
  236. * The processor supports RDSEED instruction.
  237. */
  238. #define CPU_FEATURE_RDSEED 0x04000000ULL
  239. /*
  240. * The processor supports ADCX and ADOX instructions.
  241. */
  242. #define CPU_FEATURE_ADCOX 0x08000000ULL
  243. /*
  244. * The processor is a full inorder (Silverthorne) processor
  245. */
  246. #define CPU_FEATURE_FULL_INORDER 0x10000000ULL
  247. /* Reserved feature bits which includes the unset bit CPU_FEATURE_AVX512 */
  248. #define RESERVED_CPU_FEATURE_BIT ((~(0x20000000ULL - 1)) | 0x01000000ULL)
  249. #endif