types.hpp 7.1 KB

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  1. #ifndef __OBLIVDS_TYPES_HPP__
  2. #define __OBLIVDS_TYPES_HPP__
  3. #include <tuple>
  4. #include <cstdint>
  5. #include <x86intrin.h> // SSE and AVX intrinsics
  6. #include <bsd/stdlib.h> // arc4random_buf
  7. // The number of bits in an MPC secret-shared memory word
  8. #ifndef VALUE_BITS
  9. #define VALUE_BITS 64
  10. #endif
  11. // Values in MPC secret-shared memory are of this type.
  12. // This is the type of the underlying shared value, not the types of the
  13. // shares themselves.
  14. #if VALUE_BITS == 64
  15. using value_t = uint64_t;
  16. #elif VALUE_BITS == 32
  17. using value_t = uint32_t;
  18. #else
  19. #error "Unsupported value of VALUE_BITS"
  20. #endif
  21. // Secret-shared bits are of this type. Note that it is standards
  22. // compliant to treat a bool as an unsigned integer type with values 0
  23. // and 1.
  24. using bit_t = bool;
  25. // Counts of the number of bits in a value are of this type, which must
  26. // be large enough to store the _value_ VALUE_BITS
  27. using nbits_t = uint8_t;
  28. // Convert a number of bits to the number of bytes required to store (or
  29. // more to the point, send) them.
  30. #define BITBYTES(nbits) (((nbits)+7)>>3)
  31. // A mask of this many bits; the test is to prevent 1<<nbits from
  32. // overflowing if nbits == VALUE_BITS
  33. #define MASKBITS(nbits) (((nbits) < VALUE_BITS) ? (value_t(1)<<(nbits))-1 : ~0)
  34. // The type of a register holding an additive share of a value
  35. struct RegAS {
  36. value_t ashare;
  37. // Set each side's share to a random value nbits bits long
  38. inline void randomize(size_t nbits = VALUE_BITS) {
  39. value_t mask = MASKBITS(nbits);
  40. arc4random_buf(&ashare, sizeof(ashare));
  41. ashare &= mask;
  42. }
  43. inline RegAS &operator+=(const RegAS &rhs) {
  44. this->ashare += rhs.ashare;
  45. return *this;
  46. }
  47. inline RegAS operator+(const RegAS &rhs) const {
  48. RegAS res = *this;
  49. res += rhs;
  50. return res;
  51. }
  52. inline RegAS &operator-=(const RegAS &rhs) {
  53. this->ashare -= rhs.ashare;
  54. return *this;
  55. }
  56. inline RegAS operator-(const RegAS &rhs) const {
  57. RegAS res = *this;
  58. res -= rhs;
  59. return res;
  60. }
  61. inline RegAS &operator*=(value_t rhs) {
  62. this->ashare *= rhs;
  63. return *this;
  64. }
  65. inline RegAS operator*(value_t rhs) const {
  66. RegAS res = *this;
  67. res *= rhs;
  68. return res;
  69. }
  70. inline RegAS &operator&=(value_t mask) {
  71. this->ashare &= mask;
  72. return *this;
  73. }
  74. inline RegAS operator&(value_t mask) const {
  75. RegAS res = *this;
  76. res &= mask;
  77. return res;
  78. }
  79. };
  80. // The type of a register holding a bit share
  81. struct RegBS {
  82. bit_t bshare;
  83. // Set each side's share to a random bit
  84. inline void randomize() {
  85. unsigned char randb;
  86. arc4random_buf(&randb, sizeof(randb));
  87. bshare = randb & 1;
  88. }
  89. inline RegBS &operator^=(const RegBS &rhs) {
  90. this->bshare ^= rhs.bshare;
  91. return *this;
  92. }
  93. inline RegBS operator^(const RegBS &rhs) const {
  94. RegBS res = *this;
  95. res ^= rhs;
  96. return res;
  97. }
  98. };
  99. // The type of a register holding an XOR share of a value
  100. struct RegXS {
  101. value_t xshare;
  102. // Set each side's share to a random value nbits bits long
  103. inline void randomize(size_t nbits = VALUE_BITS) {
  104. value_t mask = MASKBITS(nbits);
  105. arc4random_buf(&xshare, sizeof(xshare));
  106. xshare &= mask;
  107. }
  108. inline RegXS &operator^=(const RegXS &rhs) {
  109. this->xshare ^= rhs.xshare;
  110. return *this;
  111. }
  112. inline RegXS operator^(const RegXS &rhs) const {
  113. RegXS res = *this;
  114. res ^= rhs;
  115. return res;
  116. }
  117. inline RegXS &operator&=(value_t mask) {
  118. this->xshare &= mask;
  119. return *this;
  120. }
  121. inline RegXS operator&(value_t mask) const {
  122. RegXS res = *this;
  123. res &= mask;
  124. return res;
  125. }
  126. // Extract a bit share of bit bitnum of the XOR-shared register
  127. inline RegBS bit(nbits_t bitnum) const {
  128. RegBS bs;
  129. bs.bshare = !!(xshare & (value_t(1)<<bitnum));
  130. return bs;
  131. }
  132. };
  133. // The _maximum_ number of bits in an MPC address; the actual size of
  134. // the memory will typically be set at runtime, but it cannot exceed
  135. // this value. It is more efficient (in terms of communication) in some
  136. // places for this value to be at most 32.
  137. #ifndef ADDRESS_MAX_BITS
  138. #define ADDRESS_MAX_BITS 32
  139. #endif
  140. // Addresses of MPC secret-shared memory are of this type
  141. #if ADDRESS_MAX_BITS <= 32
  142. using address_t = uint32_t;
  143. #elif ADDRESS_MAX_BITS <= 64
  144. using address_t = uint64_t;
  145. #else
  146. #error "Unsupported value of ADDRESS_MAX_BITS"
  147. #endif
  148. #if ADDRESS_MAX_BITS > VALUE_BITS
  149. #error "VALUE_BITS must be at least as large as ADDRESS_MAX_BITS"
  150. #endif
  151. // A multiplication triple is a triple (X0,Y0,Z0) held by P0 (and
  152. // correspondingly (X1,Y1,Z1) held by P1), with all values random,
  153. // but subject to the relation that X0*Y1 + Y0*X1 = Z0+Z1
  154. using MultTriple = std::tuple<value_t, value_t, value_t>;
  155. // The *Name structs are a way to get strings representing the names of
  156. // the types as would be given to preprocessing to create them in
  157. // advance.
  158. struct MultTripleName { static constexpr const char *name = "t"; };
  159. // A half-triple is (X0,Z0) held by P0 (and correspondingly (Y1,Z1) held
  160. // by P1), with all values random, but subject to the relation that
  161. // X0*Y1 = Z0+Z1
  162. using HalfTriple = std::tuple<value_t, value_t>;
  163. struct HalfTripleName { static constexpr const char *name = "h"; };
  164. // The type of nodes in a DPF. This must be at least as many bits as
  165. // the security parameter, and at least twice as many bits as value_t.
  166. using DPFnode = __m128i;
  167. // A Select triple is a triple of (X0,Y0,Z0) where X0 is a bit and Y0
  168. // and Z0 are DPFnodes held by P0 (and correspondingly (X1,Y1,Z1) held
  169. // by P1), with all values random, but subject to the relation that
  170. // (X0*Y1) ^ (Y0*X1) = Z0^Z1. These are only used while creating RDPFs
  171. // in the preprocessing phase, so we never need to store them. This is
  172. // a struct instead of a tuple for alignment reasons.
  173. struct SelectTriple {
  174. bit_t X;
  175. DPFnode Y, Z;
  176. };
  177. // These are defined in rdpf.hpp, but declared here to avoid cyclic
  178. // header dependencies.
  179. struct RDPFPair;
  180. struct RDPFPairName { static constexpr const char *name = "r"; };
  181. struct RDPFTriple;
  182. struct RDPFTripleName { static constexpr const char *name = "r"; };
  183. // We want the I/O (using << and >>) for many classes
  184. // to just be a common thing: write out the bytes
  185. // straight from memory
  186. #define DEFAULT_IO(CLASSNAME) \
  187. template <typename T> \
  188. T& operator>>(T& is, CLASSNAME &x) \
  189. { \
  190. is.read((char *)&x, sizeof(x)); \
  191. return is; \
  192. } \
  193. \
  194. template <typename T> \
  195. T& operator<<(T& os, const CLASSNAME &x) \
  196. { \
  197. os.write((const char *)&x, sizeof(x)); \
  198. return os; \
  199. }
  200. // Default I/O for various types
  201. DEFAULT_IO(RegBS)
  202. DEFAULT_IO(RegAS)
  203. DEFAULT_IO(RegXS)
  204. DEFAULT_IO(MultTriple)
  205. DEFAULT_IO(HalfTriple)
  206. #endif